2 bit multiplier

We found following good implementations to compare:


1. Power: 228, area: 760, 122 ps maximum delay, 3 levels, max. fan-outs - 3, 8 gates, 54 transistors, 20 wires


Two gate-level netlists designed by Logic Friday system:


2. Power: 213, area: 390, 91 ps maximum delay, max. levels: 3, max fan-out: 3, 7 gates, 44 transistors, 19 wires


3. Power: 214, area: 415, 121 ps maximum delay, max. levels: 3, max fan-out: 3, 8 gates, 42 transistors, 20 wires

Our results

We used this gate setting.

Our Truth Table.

Here are all our 353 results.

Version 1. Minimum power and area:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic:
  
  
  

Version 2. Fastest version:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic: