7 segment decimal decoder

We found many implementations, but we think that our versions will overperform any other (please send us your version, if it is better)!








Gate-level netlist designed by Logic Friday system:


1. Power: 628, area: 935, 195 ps maximum delay, max. levels: 6, max fan-out: 7, 21 gates, 102 transistors, 50 wires


2. Gate-level netlist designed by Synopsys Inc. Power: 1061, area: 1885, 182 ps maximum delay, max. levels: 5, max fan-out: 8, 34 gates, 204 transistors, 75 wires
Synopsis. Design Compiler User Guide Version P-2019.03, March 2019

Our results

We used this gate setting.

Here is our Truth Table.

Here are all our 585 results.

Version 1. Minimum area:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic:
  
  
  

Version 2. Minimum power:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic:
  
  
  

Version 3. Fastest version:

• Our format
  
  
• Verilog and VHDL formats
  
  
• Schematic simulation and editing
  
  
• Schematic:
  
  
  

Our version of 7 segment decimal decoder circuit outperforms the Logic Friday (Espresso) version in several key areas:

• it reduces power consumption by 1.45 times,
• improves delay (performance) by 2.24 times,
• decreases area requirements by 1.04 times,
• cuts gate count by 1.23 times,
• reduces transistor count by 1.21 times,
• and lowers wire usage by 1.04 times.

It also outperforms the Synopsys Inc. version in several key areas:

• it reduces power consumption by 2.46 times,
• improves delay (performance) by 2.09 times,
• decreases area requirements by 2.09 times,
• cuts gate count by 2.00 times,
• reduces transistor count by 2.42 times,
• and lowers wire usage by 1.56 times.