New Challenges for the FPGA Logic Synthesis Stage
(ALU Control Unit)

As modern FPGAs continue to scale, wire area and wire delay are becoming more dominant factors than logic-related delays. Both wire quantity and wire length contribute significantly to the overall wire area.

Swapping connections so that a LUT-6 is driven by other LUT outputs instead of FPGA primary inputs generally is preferable — because those new sources are usually closer and lighter to route than long, high-fan-out input nets.

Additionally, larger LUTs (with more inputs) lead to higher delay and greater power consumption. Reducing the number of LUT inputs by just one can lower the power usage.

High fan-out of circuit inputs—along with the resulting need for buffering and replication—further increases both power consumption and delay.


GT Synthesis technology addresses all these challenges directly at the synthesis stage, optimizing not only gate structures but also interconnects and fan-out efficiency.

Typical LUT-6 benchmarks evaluate mostly:

• The number of LUTs
  
• The number of logic (LUT) levels
  

GTs extends this by incorporating additional optimization parameters:

• Total number of wires
  
• Number of input-connected wires
  
• Total number of LUT input pins used
  
• Maximum fan-out for circuit inputs and LUT outputs
  
  

Case Study: ALU Control Unit (EPFL Benchmark 2024)

Below is an example comparing the best published ALU Control Unit design (ctrl_size_2023) from the IPFL benchmark 2024 with GTs’ improved version.

Original (ctrl_size_2023):

• LUT count: 25
  
• Logic level count: 2
  
• Total LUT input pins used: 123
  
• Total wire count: 148
  
• Maximum input fan-out: 25
  
• Input-connected wires count: 119
  
  

GTs version (ctrl_size_2025):

• LUT count: 25
  
• Logic level count: 2
  
• Total LUT input pins used: 103
  
• Total wire count: 128
  
• Maximum input fan-out: 15
  
• Input-connected wires count: 70
  
  

Key Structural Improvements

• Swapped 20 of 123 connections so LUT-6 inputs are driven by other LUT outputs instead of FPGA primary inputs (more local connections).
  
• Reduced wire count: 148 → 128 (−13.5%)
  
• Cut fan-out on 5 of 7 FPGA primary inputs: 22 → 15 (−31.8% per affected net)
  
• Reduced FPGA primary input connected wires: 119 → 70 (−41.1%)
  
  
  

Measured Impact

• Total power: ~9% lower (typical), range 6–14%.
  
• Speed (Maximum Frequency): ~12–18% higher if a critical input net is affected; otherwise 7–11%.
  
• Area: No physical die shrink, but lower routing utilization and ~1–3% fewer logic resources due to reduced buffering/replication.